This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-191589, filed Jun. 26, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method for facilitating precise and stable forming and holding of a impurity profile that exists at a channel portion under a transistor gate electrode, which is essential to reduce a transistor gate length to the minimum in a technique (hereinafter, referred to as a gate prefabrication technique) for forming an element isolation region in a self alignment manner by using a transistor forming region that has been formed in advance in order to make it possible to form transistors with high concentration. This manufacturing method is applied to manufacture of peripheral transistors of an NAND-type flash memory manufactured by employing a gate prefabrication technique, for example.
2. Description of the Related Art
There has been made an attempt to form a MOS type semiconductor device, in which a part of a multilayered gate electrode, for example, a first layer is first formed in a predetermined region for forming an impurity diffusion layer and a channel portion. Then, an element isolation region is formed in a self alignment manner by employing the first layer as a mask, thereby achieving high concentration and low cost (refer to T. Ukeda et al., SSDM 1996, pp. 260-262). A description will be given with reference to FIG. 12A to FIG. 12D by way of showing this conventional attempt. First, a N-Well 103 and P-Well 102 are formed on a P-type silicon substrate 101, and a SiO2 film 104 is formed on the P type silicon substrate 101. Further, using a resist pattern (not shown) as a mask converting the P-Well 102, a boron xe2x80x9cBxe2x80x9d ion 105 is implanted onto the N-Well 103 in order to perform P type transistor channel control. Furthermore, with the resist pattern 106 being employed as a mask, a xe2x80x9cBxe2x80x9d ion 107 is implanted on the P-Well 102 in order to perform N type transistor channel control.
Next, after removing the SiO2 film 104, a gate oxide film 108 is formed by thermal oxidization, and a polysilicon film 109 is formed (FIG. 12B). At this time, the boron xe2x80x9cBxe2x80x9d ions implanted for the purpose of transistor channel control shown in FIG. 12A are activated, and diffuses into the P type silicon substrate 101 as impurity diffusion regions 105xe2x80x2 and 107xe2x80x2, respectively, as shown in FIG. 12B.
Next, the polysilicon film 109 that exists in a desired element isolation region is etched off; and the SiO2 film 108 and P type silicon substrate 101 are etched off to form a trench 110T. The SiO2 film 110 is buried in the thus formed trench 110T by a CVD technique, as shown in FIG. 12C, and then, heat treatment is applied to the buried film. The heat treated film is flattened using a CMP method, and the silicon oxide film remaining on the polysilicon film 109 is etched away.
Next, a polysilicon film 111 is formed on the SiO2 film 110 buried in the trench 110T and on the polysilicon film 109, and then, a resist pattern 112 is formed on a predetermined region of the polysilicon film 111 for forming a gate electrode wiring layer. At this time, it is well known that a high temperature densifying step is required because there is a need to increase concentration of the SiO2 film 110 in order to function the film 110 buried in the trench 110T as an insulation film for element isolation. The SiO2 film 110 is not a thermal oxide film, but a sintered CDV film.
With this heating step, the boron xe2x80x9cBxe2x80x9d impurities introduced into the silicon substrate 101 for the purpose of transistor channel control further diffuses deeply into the silicon substrate 101, and impurity diffusion regions 105xe2x80x3 and 107xe2x80x3 are formed, respectively, as shown in FIG. 12C.
Next, using the resist pattern 112 as a mask, the patterns of the polysilicon film 111 and polysilicon film 109 are formed by an etching process. Then, after releasing the resist pattern 112, a step of forming an LDD region 113, a step of forming a side wall 114 of a gate electrode, and a step of forming a diffusion layer 116 are carried out. Further, an N type transistor and a P type transistor are formed through a post-oxidization step at 800xc2x0 C. and for about 600 minutes. Of course, at this heating step as well, the impurity of boron xe2x80x9cBxe2x80x9d slightly introduced into the silicon substrate 101 diffuses over the wide area of the silicon substrate 101.
A semiconductor device manufactured in accordance with the above described steps is formed in a self alignment manner together with the channel portion and diffusion layer area that configure transistors. Thus, an element isolation region can be formed to have a minimum size. Therefore, this technique can be essential in forming a transistor with high concentration.
In contrast, there occurs a disadvantage that a channel length of a transistor cannot be reduced to the minimum for the reasons described below. Of course, it is required to reduce the channel length to the minimum in order to miniaturize a transistor and provide a high element concentration. In order to reduce the channel length to the minimum, it is essential to control the transistor channel profile. For example, in general, in an buried channel P type transistor which is widely used, as is well known, it is effective to set this buried channel closer to the silicon substrate surface. However, it is necessary to provide a sharp impurity profile in order to achieve this channel positioning. In addition, in an NMOS as well, it is well known that a better controlled profile is effective.
Hence, in the conventional example shown in FIG. 12A to FIG. 12D, an element isolation region is manufactured in a self alignment manner with respect to a transistor forming region, and thus, the element isolation region can be finely manufactured. However, from the reasons described previously, with respect to a transistor channel length, it is very difficult to realize it due to the difficulty of the channel impurity profile control. Thus, there is a disadvantage that the transistor channel length cannot be reduced to the minimum, and the transistor forming region occupies a large area on a chip. Hereinafter, the reasons will be described in detail.
Conventional semiconductor device manufacturing steps widely employed include the steps of: providing an element isolation insulation film on the surface of a substrate; introducing impurities for the purpose of transistor channel control; forming a gate insulation film; and forming a gate electrode of a transistor.
In contrast, the prior art process steps shown in FIG. 12A to FIG. 12D include the steps of: introducing impurities for the purpose of transistor channel control; forming a gate insulation film; forming a part of a gate electrode; and forming an element isolation insulation film. Thus, the heating step after introducing impurities for the purpose of transistor channel control additionally is included in the step of forming an element isolation insulation film. This heating step is carried out at 850xc2x0 C. and for about 30 minutes, for example. With this heating step, impurities added for the purpose of transistor channel control diffuse unnecessarily and significantly into the substrate, which makes it difficult to perform precise channel profile control. This leads to impairment of reducing the transistor channel length to the minimum.
In addition, if the transistor channel profile cannot be controlled as a desired steep profile, it is known that the following failure will occur in addition to the impairment of reducing the transistor channel length to the minimum. For example, in the case where xe2x80x9cB (boron)xe2x80x9d added for the channel control is further diffused as P type impurities in an N type transistor forming region, the spread in the depth direction of the substrate causes a rise in threshold value Vth due to an increase in substrate bias effect. It is a well known fact that this rise causes an impairment when a transistor circuit is operated at a high speed. In order to minimize this disadvantage, it is known that the concentration of impurities near the surface of a silicon substrate is increased. In the conventional example shown in FIG. 12A to FIG. 12D, the heating time and temperature after introducing impurities are excessive, and thus, the degree of the impurity diffusion is also excessive. Therefore, an increase in back bias effect cannot be avoided, which causes a defect in high speed circuit operation.
As a technique for avoiding such defect caused by the heating step, there is considered a technique for introducing impurities for transistor channel control after forming a gate electrode, by means of ion implantation, for example. However, even if such technique is employed, a limitation is applied to introduction of this technique for the following reasons, and desired steep profile control is not possible.
In general, boron whose ion mass is comparatively light is used as impurities for transistor channel control. When ion mass is light, and acceleration energy is large, it is well known that an impurity profile during ion implantation spreads (Reference: Seijiro Furukawa, Semiconductor Device, Corona Co., Ltd. pp. 57-58: S. M Sea, Supervized Translated by: Takeishi, Nishi, Kayama, Ultra-LSI Technology, Soken Shuppan, pp. 231-236).
In a technique for introducing impurities for transistor channel control after forming a gate electrode, if the film thickness of the gate electrode is large, a boron ion is implanted under acceleration energy conditions required for penetrating the thick gate electrode material and gate oxide film. Therefore, although the diffusion of boron impurities at the heating step can be avoided, a wide spread profile is formed by scattering during ion implantation. This makes it difficult to perform desired profile control.
Although it is considered to reduce the film thickness of the gate electrode, reducing the thickness of the gate electrode or the gate wiring layer causes an increase in wiring resistance, resulting in a degradation of high speed element operation. Thus, a polysilicon film of about 400 nm or more in thickness is required to achieve a required sheet resistance Rs=100 xcexa9/xe2x96xa1 or less. In this case, high acceleration energy for the ion implantation is required to inject ions into a silicon substrate through a polycrystalline silicon of about 400 nm in thickness. However, as described above, production of such a desired profile is difficult because of ion scattering during such a high energy implantation.
In addition, in recent years, a demand for an electrically erasable programmable nonvolatile memory device is increasing in market. However, an increase in transistor substrate back bias effect causes a defect in high speed circuit operation in such a nonvolatile memory device, and causes in increase of a size of a boost power supply circuit. This is one of the problems to be solved.
The reason is briefly described as follows. In a circuit configuring an electrically erasable programmable nonvolatile memory device, when data write/erase operation is electrically performed for a memory cell transistor, it is general to employ a circuit configuration in which a plurality of power supplies are internally provided based on an external power supply voltage.
For example, an NAND type flash memory device is used as an electrically erasable programmable nonvolatile memory device. In this case, an internal power supply is provided for producing 20 volts from an external power supply voltage of 5 volts. A charge pump is conventionally used as an available voltage boosting circuit system (see an article supervised by Takuo Sugano and edited by Tetsuya Iizuka: Design of CMOS ultra-LSI, Baifu-kan, pp. 192-193). In this case, however, if a substrate back bias effect of a transistor forming a boost circuit for carrying out the charge pumping is large, the boost efficiency will be degraded. Thus, the boost circuit is increased in size, and therefore, the chip size is increased. Therefore, in order to ensure boost efficiency, it is essential to use a transistor with its minimized back bias effect. In particular, the NAND type flash memory device using an external source voltage of 5 volts, for example, requires a write/erasure voltage of 20 volts, and the problem is more serious.
According to one aspect of the present invention, there is provided a semiconductor device manufacturing method comprising:
forming a gate oxide film of a MOS type transistor on a semiconductor substrate;
forming a conductive film that configures a part of a gate electrode on the gate oxide film; and
implanting impurities in the semiconductor substrate through the conductive film and gate oxide film.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising:
forming a gate oxide film of a MOS type transistor on a semiconductor substrate;
forming a conductive film that configures a part of a gate electrode on the gate oxide film;
removing the gate oxide film and conductive film formed on a predetermined region for forming an element isolation region;
forming a trench in the semiconductor substrate;
burying an element isolation oxide layer in the trench; and
implanting impurities into the semiconductor substrate through the conductive film and gate oxide film.
With this configuration, desired profile control can be achieved as compared with a conventional semiconductor device in which a desired transistor channel control has been difficult. In the manufacture of an N type transistor, a back bias effect is significantly restricted, and such effect causes a Vth rise of about ⅔ as compared with a conventional device. In addition, a short channel effect/punch through leak is restricted, the gate length is reduced to the minimum.
In addition, in the manufacture of a P type transistor, the gate length can be reduced by about 0.1 xcexcm. Therefore, a semiconductor device with high speed, high performance, and high concentration can be achieved. In particular, a two-layer gate electrode type transistor is employed as a memory cell, and an electrode terminal using a contact plug is formed at a first gate electrode of a two-layer gate electrode via a gate insulation film provided on a semiconductor substrate, which is preferably applicable to a semiconductor device of such a type functioning as a general transistor. In addition, in the case where the two-layer gate electrode type transistor and memory cell are formed on the same substrate, there exists an N type transistor to which a high potential is applied during write/erase operation. The present invention is applied to an N type transistor to which the high potential is applied. As a result, a back bias effect is significantly restricted, and transfer efficiency in a charge pump circuit is improved, making it possible to reduce the chip size.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.